1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a MOS static type semiconductor memory device the load element thereof consisting of a P-channel type thin film transistor (TFT).
2. Description of the Prior Art
There are two kinds of memory cells, namely, a high load resistance type memory cell and a CMOS type memory cell in a MOS static type semiconductor memory cell (referred to as an SRAM hereinafter). A high load resistance type memory cell is constituted of a pair of high load resistance elements, a pair of driver transistors, each consisting of an N-channel MOS transistor, and a pair of access transistors each consisting of an N-channel MOS transistor. The respective one ends are connected to a power supply wiring, the other ends of these high load resistance elements are connected respectively to the drain regions of the driver transistors, and the respective source regions of these driver transistors are connected to a grounding wiring. The pair of driver transistors are coupled to form a flip-flop circuit. The source regions of the pair of access transistors are respectively connected to the drain regions of these driver transistors, a word line is connected to the gate electrodes of the access transistors, and a pair of digit lines are connected respectively to the drain regions of the access transistors.
The CMOS type memory cell is constituted by a pair of load transistors, each consisting of a P-channel MOS transistor, a pair of driver transistors each consisting of an N-channel MOS transistor, and a pair of access transistors each consisting of an N-channel MOS transistor. A pair of CMOS inverters constituted of these two load transistors and these two driver transistors are coupled to form a flip-flop circuit. In the CMOS inverter, the drain region of the load transistor is connected to the drain region of the driver transistor, the gate electrode of the load transistor is connected to the gate electrode of the driver transistor, the source region of the load transistor is connected to the power supply wiring, and the source region of the driver transistor is connected to the grounding wiring. The connection relationship of the source region, the drain region, and the gate region is the same as for the high load resistance memory cell.
When a polycrystalline silicon film is used as the high load resistance element in the high load resistance type memory cell, the area of the memory cell is smaller than the area of the CMOS type memory cell due to the fact that the high load resistance element is formed above the driver transistor and the like via an insulating film and that the number of the nodes is small compared with the case of the CMOS type memory cell. In other words, the high load resistance type memory cell is advantageous for reduction of the area of the memory cell (cell size). On the other hand, the CMOS type memory cell is advantageous over the high load resistance type memory cell in that the value of the off-current is smaller than that of the on-current. In other words, the standby current of the CMOS type memory cell is smaller than the other. The new SRAM has drawn attention in recent years as a back-up memory for an electronic notebook, gaming apparatus, or the like. Batteries are used as the back-up power supply with these memories being operated by a low voltage power supply of 1.5 to 3V, and it becomes important that the standby current is low. TFTs are beginning to be adopted as the P-channel MOS transistor for the load transistor, for the purpose of reducing the area of the CMOS type memory cell (such a memory cell will be referred to as a TFT type memory cell hereinafter).
In an SRAM having TFT type memory cells, the formation of the power supply wiring, the grounding wiring, the word line, and the pair of digit lines that are to be connected to one memory cell, the formation of one memory cell from its constituent elements of four N-channel MOS transistors and two P-channel type TFTs, the mutual connection between these transistors, and the connection between these transistors and the wirings are realized by means of a plurality of layers of electrical conduction film or the like. Although there are many alternatives available for construction of the respective wirings and the component elements, the respective connections, or the like, the general construction is done as in the following.
These N-channel MOS transistors are respectively formed on the surface of a silicon substrate, and the respective gate electrode and the word line of these transistors are formed of a first layer of conductor film. The grounding wiring is formed of a second layer of conductor film in order for it to be connected to the source region of the driver transistor, and in order to avoid crossing with the gate electrode and the word line within the same memory cell and the crossing with the connecting wirings between the TFT and these N-channel MOS transistors. The TFTs are formed of a third and fourth layers of conductor films. The first and the second layers of conductor films are respectively made of an N.sup.+ -type polycrystalline silicon film or a high melting point metallic film or a silicide film or a polycide film. The gate electrode of the TFT is formed of either one of the third or the fourth conductor film. This conductor film is a P.sup.+ -type polycrystalline silicon film or an N.sup.+ -type polycrystalline silicon film or a high melting point metallic film or a silicide film or a polycide film. The power supply wiring serves also as the source region of the TFT. Its drain region and the channel region are formed of the other of the third and the fourth layers of conductor film. This conductor film consists of a polycrystalline silicon film where it is a P.sup.+ -type polycrystalline silicon film except for the channel region. The first, the second, the third, and the fourth layers of conductor film consist of materials that have melting point higher than that of aluminum. The digit line is formed of an aluminum film.
The reason for forming the digit lines using an aluminum film is the following. In general, the value of the current that flows in the four kinds of wirings is the largest for the grounding wiring followed by the digit line and the power supply wiring, and hardly any current flows in the word line. The digit line is a signal line, and since the signal is detected with a sense amplifier, the digit line is required to have a low resistance in particular. For this reason, it is usual to form the digit line of a low resistance material, such as aluminum film.
The grounding wiring is not formed of an aluminum film for the following reason. The digit lines are provided with a high density approximately parallel in a prescribed direction, and the spacing between a pair of digit lines in the above becomes one factor for specifying the cell size. For example, if the grounding wirings are aluminum films, it increases the spacing of the pair of digit lines and makes the cell size larger, opposing the trend for miniaturization of the semiconductor device.
A SRAM having TFT memory cells of the aforementioned structure is disclosed in, for example, Japanese Patent Laid Open No. 202858-1989. First, the constitution of the circuit will be described. The memory cell of the (m, n) bit is constituted of a first and a second access transistors consisting of an N-channel MOS transistor, a first and a second driver transistors consisting of an N-channel MOS transistor, first and a second P-channel load transistor TFTs, a first and second digit lines of the m-th column, a word line of the n-th row, a power supply wiring, and a grounding wiring. The word line is connected to the respective gate electrodes of the first and the second access transistors, and the first and the second digit lines are connected to the drain regions of the first and the second access transistors, respectively. A first CMOS inverter is constituted of the first TFT and the first driver transistor, a second CMOS inverter is constituted of the second TFT and the second driver transistor, and the first CMOS inverter and the second CMOS inverter are coupled to form a flip-flop. The power supply wiring is connected to the respective source regions of the first and the second driver transistors. The source region of the first access transistor is connected to the drain region of the first driver transistor. The source region of the second access transistor is connected to the drain region of the second driver transistor. Diodes of the P-N junction are formed respectively between the drain region of the first TFT and the drain region of the first driver transistor, and between the drain region of the second TFT and the drain region of the second driver transistor.
Next, the device of the memory cell of the (m, n) bit of the SRAM disclosed in the above-mentioned Laid Open Japanese Patent application will be described. The first and second access transistors and the first and second driver transistors are formed, respectively, on the surface of the P-type region of the silicon substrate. The respective gate electrodes of the first and the second driver transistors and the word line for the n-th row are formed by an N.sup.+ -type polycrystalline silicon film of the first layer. This word line also serves as the gate electrodes of the first and the second access transistors. An N.sup.+ -type diffused layer, which is the source region of the first access transistors, and an N.sup.+ -type diffused layer which is the drain region of the first driver transistor are connected by the gate electrode of the second driver transistor via a connecting hole reaching an N.sup.+ -type diffused layer which is the source region of the first access transistor and a connecting hole reaching an N.sup.+ -type diffused layer which is the drain region of the first driver transistor. The source region of the second access transistor and the drain region of the second driver transistor are formed of the same N.sup.+ -type diffused layer. The gate electrode of the first driver transistor is connected to this N.sup.+ -type diffused layer via a connecting hole that reaches this N.sup.+ -type diffused layer.
A first grounding wiring which is the grounding wiring within the memory cell is formed of an N.sup.+ -type polycrystalline silicon film of the second layer. The first grounding wiring is connected to the N.sup.+ -type diffused layers, which are the respective source regions of the first and second driver transistors, via the connecting holes which reach the respective N.sup.+ -type diffused layers that are the source regions of the first and the second driver transistors. The source regions of the first and the second driver transistors are made common to the source region of the second driver transistor for the bit (m+1, n) and the source region of the first driver transistor for the bit (m-1, n), respectively. Because of this, the above-mentioned two connecting holes are provided on the boundary of the region for the bit (m+1, n) and the region for the bit (m,n), and on the boundary of the region for the bit (m,n) and the region for the bit (m-1, n), respectively. The first grounding wiring extends to the region for the bit (m-1, n) in the vicinity of the connecting hole that reaches the N.sup.+ -type diffused layer which is the source region of the second driver transistor of the (m,n) bit. Similarly, the first grounding wiring extends to the region of the (m+1, n) bit in the vicinity of the connecting hole that reaches the N.sup.+ -type diffused layer which is the source region of the first transistor for the bit (m,n), and extends in the direction that includes the boundary of the region for the bit (m, n-1) and the region for the bit (m-1, n-1). From these facts, the first grounding wiring for the bits belonging to the (n-1)-th row and for the bits belonging to the n-th row is common to both. Similarly, the first grounding wiring for the bits belonging to the (n+ 1)-th row and for the bits belonging to the (n+2)-th row is common to both. A P.sup.+ -type diffused region which is the source region's and the power supply wirings of the first and the second TFTs, and the P.sup.+ -type diffused regions which are the respective channel regions of the first and the second TFTs, and the respective drain regions of the first and the second TFTs are formed by a third layer of polycrystalline silicon film. The P.sup.+ -type diffused region which is the drain region of the first TFT is connected to the N.sup.+ -type diffused layer which is the source region of the first access transistor and the gate electrode of the second driver transistor via the connecting holes that reach the N.sup.+ -type diffused layer which is the source region of the first access transistor and the gate electrode of the second driver transistor. Similarly, the P.sup.+ -type diffused region which is the drain region of the second TFT is connected to the N.sup.+ -type diffused layer which is the source region of the second access transistor and the gate electrode of the first driver transistor via the connecting holes that reach the N.sup.+ -type diffused layer which is the source region of the second access transistor and the gate electrode of the first driver transistor. These two connecting holes are provided in the regions free from the first grounding wiring.
The respective gate electrodes of the first and the second TFTs are formed by a fourth layer of N.sup.+ -type polycrystalline silicon film. The gate electrode of the first TFT is connected, via a connecting hole that reaches the N.sup.+ -type diffused layer which is the sourde region of the second access transistor as well as the drain region of the second driver transistor, to this N.sup.+ -type diffused layer. By so doing, the gate electrode of the first TFT becomes to be connected also to the gate electrode of the first driver transistor. The gate electrode of the second TFT is connected to the N.sup.+ -type diffused layer which is the gate electrode as well as the drain region of the first driver transistor, via a connecting hole which reaches the N.sup.+ -type diffused layer that is the gate electrode of the second driver transistor and the drain region of the first driver transistor. By so doing, the gate electrode of the second TFT becomes connected also to the N.sup.+ -type diffused layer which is the source region of the first access transistor. These two connecting holes are formed in the regions free from the first grounding wiring. It should be noted that, for example, the reason for providing the connecting hole that connects the N.sup.+ -type diffused layer which is the drain region of the second driver transistor and the P.sup.+ -type diffused layer which is the drain region of the second TFT, and the connecting hole that connects the N.sup.+ -type diffused layer which is the drain region of the second driver transistor and the gate electrode of the first TFT, at positions apart from each other, is to avoid the formation of an N-P-N junction.
The first and the second digit lines made of an aluminum film are connected to the N.sup.+ -type diffused layer which are the drain regions of the first and the second access transistors, respectively, via the connecting holes that reach respectively the N.sup.+ -type diffused layers that are the drain regions of the first and the second access transistors. These connecting holes are formed in the regions free from the first grounding wiring. The N.sup.+ -type diffused layers which are the drain regions of the first and the second access transistors are also the drain regions of the first and the second access transistors, respectively, for the bit (m, n+1). In other words, the connecting holes that connect the respective digit lines and the drain regions of the access transistors at a bit belonging to the n-th row and at a bit belonging to the (n+1)-th row are common. Further, these connecting holes are provided in a line on the boundary of the region for the bits belonging to the n-th row and the region for the bits belonging to the (n+1)-th row. Similarly, the connecting holes that connect the digit lines and the drain regions of the access transistors are formed respectively in a line on the boundary between the region for the bits belonging to the (n-2)-th row and the region for the bits belonging to the (n-1)-th row, on the boundary between the region for the bits belonging to the (n+2)-th row and the region for the bits belonging to the (n+3)-th row, and the like.
Because of the above, the first grounding wiring cannot traverse the boundary between, for example, the region for the bits belonging to the n-th row and the region for the bits belonging to the (n+1)-th row. In deciding the region that is acceptable for providing the first grounding wiring it is necessary to consider, besides the connecting hole that connects the digit line and the drain region of the access transistor, a pair of CMOS inverters which consist of the first and the second driver transistors and the first and the second TFTs and the four connecting holes for constructing a flip-flop circuit out of these inverters. As a result, the first grounding wiring for this case has a ladderlike shape which extends in the direction approximately parallel to the word line.
As described in the above, the current that flows in the grounding wiring is larger than the current that flows in other wirings (namely, the digit line, the power supply wiring, and the word line) so that it is desirable that the first grounding wiring has a low resistance. This is particularly important in reading each bit. Suppose that the bit (m,n) the drain region of the first driver transistor is written at a High level and the drain region of the second driver transistor is written at a Low level. At this time, the word line of the n-th row is at Low and the first and the second digit lines of the m-th column are respectively at High. In order to read the state written as in the above the word line is made to go from Low to High, and the second digit line is made to go from High to Low. Since the second access transistor is energized at this time (note that the second driver transistor has been energized), there occurs a discharge from the second digit line through the first grounding wiring to the second grounding wiring made of an aluminum film. The change with time of this discharge is detected by a sense amplifier as the change with time of the potential difference between the first digit line and the second digit line. Because of this, if the resistance of the first grounding wiring is high, the apparent variation voltage from High to Low becomes small due to the voltage drop, and the change with time of the discharge is relaxed. That is to say, the sensitivity of detection by the sense amplifier is reduced. Moreover, if, for the same bit, the resistance of the first grounding wiring between the source region of the first driver transistor to the second grounding wiring is different from the resistance of the first grounding wiring between the source region of the second driver transistor and the second grounding wiring, the detection sensitivity of (High, Low) and the detection sensitivity of (Low, High) for the same bit become different.
The first grounding wiring formed of the second layer of polycrystalline silicon film is connected for every 16 bits, for example, to the low resistance second grounding wiring formed of an aluminum film. The second grounding wiring is provided in parallel with the digit line formed of an aluminum film. Assume that the resistances of the first grounding wiring between a connecting hole that connects the source region of the driver transistor and the first grounding wiring and the adjacent two connecting holes are all equal to R. The resistance of the first grounding wiring for the portion from this connecting hole provided on the boundary between the bit (m-1, n) and the bit (m,n) to the second grounding wiring formed of the aluminum film, becomes a function, R(m), of m. A simulation for the resistance value of the first grounding wiring with the above-mentioned shape under such an assumption produced a result that R(1)=R(16)=0.6R, R(2)=R(15)=1.2R, . . . , R(4)=R(13)=1.9R, R(6)=R(11)=2.2R, and R(8)=R(9)=2.4R. As is clear from this result, the detection sensitivity of read at the bit for m=8 is markedly low compared with that at the bit for m=1. In addition, the detection sensitivity for (Low, High) is reduced compared with the detection sensitivity for (High, Low) since R(1)/R(2) is about 1/2 at the bit for m=1.
Accordingly, if the shape of the first grounding wiring formed of the second layer of polycrystalline silicon film is ladderlike, as was mentioned above, the resistance of the first grounding wiring for the portion from the specified connecting hole to the second grounding wiring formed of the aluminum film has a maximum range of variation of a factor of four. From this it follows that the detection sensitivity of read at the bit for m=8 is lower than that at the bit for m=1. Similarly, at the bit for m=16, the detection sensitivity for (High, Low) becomes lower than the detection sensitivity for (Low, High). Furthermore, the potential for write at High level is specified by the voltage of the power supply, so that the problem of reduction in the detection sensitivity becomes a matter of grave concern when a power supply with low voltage is employed.
The TFT described in the aforementioned Japanese Laid Open Patent application is of the top gate type and the portion between the channel region of the first TFT and the gate electrode of the second driver transistor and the portion between the channel region of the second TFT and the gate electrode of the first driver transistor are almost shielded by the first grounding wiring formed of the second layer of polycrystalline silicon film. However, this shielding is not intentional, and it is difficult to completely shield the portion between the channel region of the first TFT and the gate electrode of the second driver transistor and the portion between the channel region of the second TFT and the gate electrode of the first driver transistor by the first grounding wiring without causing an increase in the cell size because there are required spacings between the connecting holes that connect the first and the second TFTs to the first and the second driver transistors and the first grounding wiring. Now, the P.sup.+ -type diffused region which is the drain region of the first TFT and the gate electrode of the second driver transistor have the equal potential, and the P.sup.+ -type diffused region which is the drain region of the second TFT and the gate electrode of the first driver transistor have the equal potential. In the portion where the above-mentioned shielding is absent, the channel region of a TFT is influenced (in inverse proportion to such things as the film thickness of the interlayer insulating film provided between the first layer of polycrystalline silicon film and the third layer of polycrystalline silicon film) by the potential of the drain region of the same TFT. In other words, the effective channel length of the TFT is reduced, and the leakage characteristic of the TFT is deteriorated (generating an increase in the leakage current at the off time of the TFT, an increase in the standby current of the SRAM, a reduction in the holding characteristic of the memory cell, and the like).
Differing from the case of the aforementioned Japanese Laid Open Patent application, in a TFT of the bottom gate type (for example, by forming a gate electrode using the third layer of polycrystalline silicon film and forming the source and the drain regions and the channel region using the fourth layer of polycrystalline silicon film), there is an advantage in making the channel length greater than the gate length, to improve the leakage characteristic by providing an off-set part by extending the channel gate from directly above the gate electrode in the direction of the drain region. Even in a memory cell which employs a P-channel type TFT of the bottom gate type as a load transistor, the first TFT, for example, is provided almost directly above the second driver transistor via an interlayer insulating film in order to comply with the demand for reduction of the cell size. When the shielding is absent for the portion between the off-set part of the channel region of the first TFT and the gate electrode of the second driver transistor, the above-mentioned influence becomes particularly conspicuous, depriving the advantage of the improvement of the leakage characteristic to a large extent.